1. Field of the Invention
This invention relates to a semiconductor package and a method for producing the same.
2. Description of Related Art
Up to now, as a semiconductor package, there is an area array BGA (ball grid array) 70 for surface mounting for an LSI (large scale integrated circuit) including a An solder ball terminal on its mounting surface to a printed wiring board, as shown in FIG. 1.
This BGA 70 includes a semiconductor device 73, including a first insulating substrate 72 and mounted on this first insulating substrate 72, and a second insulating substrate 75, layered via a prepreg 74 on the first insulating substrate 72, as shown in FIG.1.
The first insulating substrate 72 is a copper-lined layered plate, comprised of e.g., a glass cloth as a base, which is impregnated with an epoxy resin and on both sides of which are bonded copper foils, with the first insulating substrate 72 being formed to substantially a rectangular shape. The first insulating substrate 72 has an electrically conductive pattern 76 formed on its one surface and has a solid pattern for a heat radiation plate 77 formed on its other surface by a print etching method employing the photolithographic technique. This first insulating substrate 72 includes a mounting portion 79 mounting a semiconductor device 73 at its mid portion. On the rim of the mounting portion 79 of the first insulating substrate 72 is layered a second insulating substrate 75 having an opening 80 for mounting the semiconductor device 73 on the first insulating substrate 72 via a prepreg 74 having an opening 81. The opening 80 is formed by punching the mid portion of the second insulating substrate 75, whilst the opening 81 is formed by punching the mid portion of the prepreg 75. In the first insulating substrate 72, a cavity 82 is formed by this opening 80 and the first insulating substrate 72. On the mounting portion 79 of the first insulating substrate 72 is mounted the semiconductor device 73 with a thermally curable adhesive, such as the die bonding agent 83, through the cavity 82. The semiconductor device 73 is electrically connected with an electrically conductive pattern 76 formed in the first insulating substrate 72 and with the bonding wire 84. The cavity 82 is coated with a liquid encapsulating resin 86 and cured by a thermal process. This planarizes the upper surface of the cavity 82 which is made flush with the upper surface of the second insulating substrate 75 to enable the BGA to be mounted precisely on a motherboard.
On one surface of the second insulating substrate 75, layered on the first insulating substrate 72, there is lined a copper foil which is patterned by a print etching method employing the photolithographic technique to form solder lands 88 and an electrically conductive pattern 89 electrically connecting the solder lands 88. Plural such solder lands 88 are formed around the opening 80 on one surface of the second insulating substrate 75.
In the, second insulating substrate 75, a plated through-hole 91 is bored for extending from the upper surface of the second insulating substrate 75 up to the lower surface of the first insulating substrate 72. Thus, the electrically conductive pattern 89, formed on the second insulating substrate 75, the electrically conductive pattern 76 formed on the first insulating substrate and the solid pattern for the heat radiation plate 77 formed on the other surface of the first insulating substrate are electrically connected via the through-hole 91. With the BGA 70, plural solder balls 92 are formed by printing cream solder on each solder land 88.
On the surface of the first insulating substrate 72 carrying the solid pattern for the heat radiation plate 77, there is bonded a heat radiating plate 93 via an adhesive. This permits heat occasionally stored in the BGA 70 to be dissipated through the heat radiating plate 93 to prevent overheating of the BGA 70.
The BGA 70 is mounted on the motherboard by the solder balls 92 formed on the upper surface of the second insulating substrate 75 to be electrically connected to the electrically conductive layer formed on the motherboard.
Meanwhile, in an electrical equipment, required to be reduced in size and weight, the BGA, enclosed therein, needs to be reduced in size. However, in a package in which an area for a cavity 82 coated with a sealed resin 86 and an area of the second insulating substrate 75, the solder balls 92 and the conductor pattern may be provided solely on the upper side of the second insulating substrate 75, while they cannot be provided on the cavity 82, thus increasing the package area. Moreover, since the function of the solder balls and the conductor patterns provide for electrical connection between the semiconductor package and the motherboard, limitations are imposed on reducing. the mounting area to render it difficult to reduce the package size.